? semiconductor components industries, llc, 2014 july, 2014 ? rev. p0 1 publication order number: NVGS4141N/d NVGS4141N product preview power mosfet 30 v, 7.7 a, single n?channel, tsop?6 features ? low r ds(on) ? low gate charge ? aec?q101 qualified and ppap capable ? these devices are pb?free, halogen free/bfr?free and are rohs compliant applications ? load switch ? notebook pc ? desktop pc maximum ratings (t j = 25 c unless otherwise noted) rating symbol value unit drain?to?source v oltage v dss 30 v gate?to?source v oltage v gs 20 v continuous drain current (note 1) steady state t a = 25 c i d 5.4 a t a = 85 c 4.2 t 10 s t a = 25 c 7.7 power dissipation (note 1) steady state t a = 25 c p d 1.2 w t 10 s 2.4 continuous drain current (note 2) steady state t a = 25 c i d 3.8 a t a = 85 c 3.0 power dissipation (note 2) t a = 25 c p d 0.61 w pulsed drain current t p = 10 s, v gs =10v i dm 22 a operating junction and storage temperature t j , t stg ?55 to 175 c source current (body diode) i s 1.2 a lead temperature for soldering purposes (1/8 from case for 10 s) t l 260 c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. thermal resistance ratings rating symbol max unit junction?to?ambient ? steady state (note 1) r ja 125 c/w junction?to?ambient ? t 10 s (note 1) r ja 62.5 junction?to?ambient ? steady state (note 2) r ja 248 1. surface?mounted on fr4 board using 1 inch sq pad size (cu area = 1.127 in sq [1 oz] including traces). 2. surface?mounted on fr4 board using the minimum recommended pad size (cu area = 0.0773 in sq). this document contains information on a product under development. on semiconductor reserves the right to change or discontinue this product without notice. tsop?6 case 318g style 1 marking diagram vs4 m vs4 = device code m = date code = pb?free package (note: microdot may be in either location) pin assignment 3 gate 1 drain source 4 2 drain drain 5 drain 6 http://onsemi.com device package shipping ? ordering information NVGS4141Nt1g tsop?6 (pb?free) 3000/tape & ree l ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. 30 v 30 m @ 4.5 v 21.5 m @ 10 v r ds(on) typ 7.7 a i d max v (br)dss 1256 3 4 drain gate source n?channel 1
NVGS4141N http://onsemi.com 2 electrical characteristics (t j = 25 c unless otherwise noted) characteristic symbol test condition min typ max unit off characteristics drain?to?source breakdown voltage v (br)dss v gs = 0 v, i d = 250 a 30 v drain?to?source breakdown voltage temperature coefficient v (br)dss /t j 18.4 mv/ c zero gate voltage drain current i dss v gs = 0 v, v ds = 24 v t j = 25 c 1.0 a t j = 125 c 10 gate?to?source leakage current i gss v ds = 0 v, v gs = 20 v 100 na on characteristics (note 3) gate threshold voltage v gs(th) v gs = v ds , i d = 250 a 1.0 3.0 v negative threshold temperature coefficient v gs(th) /t j 5.7 mv/ c drain?to?source on resistance r ds(on) v gs = 10 v, i d = 7.0 a 21.5 25 m v gs = 4.5 v, i d = 6.0 a 30 35 forward transconductance g fs v ds = 10 v, i d = 7.0 a 30 s charges, capacitances and gate resistance input capacitance c iss v gs = 0 v, f = 1.0 mhz, v ds = 24 v 560 pf output capacitance c oss 115 reverse transfer capacitance c rss 75 total gate charge q g(tot) v gs = 10 v, v ds = 15 v, i d = 7.0 a 12 nc threshold gate charge q g(th) 0.85 gate?to?source charge q gs 1.9 gate?to?drain charge q gd 3.0 total gate charge q g(tot) v gs = 4.5 v, v ds = 15 v, i d = 7.0 a 6.0 nc threshold gate charge q g(th) 0.8 gate?to?source charge q gs 1.85 gate?to?drain charge q gd 3.0 gate resistance r g 2.8 switching characteristics (note 4) turn?on delay time t d(on) v gs = 10 v, v ds = 24 v, i d = 7.0 a, r g = 3.0 6.0 ns rise time t r 15 turn?off delay time t d(off) 18 fall time t f 4.0 drain ? source diode characteristics forward diode voltage v sd v gs = 0 v, i s = 2.0 a t j = 25 c 0.78 1.0 v t j = 125 c 0.63 reverse recovery time t rr v gs = 0 v di s /dt = 100 a/ s, i s = 2.0 a 15 ns charge time t a 9.0 discharge time t b 6.0 reverse recovery charge q rr 8.0 nc 3. pulse test: pulse width 300 s, duty cycle 2%. 4. switching characteristics are independent of operating junction temperatures.
NVGS4141N http://onsemi.com 3 typical performance curves 125 c 0 15 8 v ds , drain?to?source voltage (volts) i d, drain current (amps) 0 figure 1. on?region characteristics 1 10 23 0 figure 2. transfer characteristics v gs , gate?t o?source voltage (volts) 15 100 10 figure 3. on?resistance vs. gate?to?source voltage v ds , drain?to?source voltage (volts) i dss, leakage current (na) i d, drain current (amps) 010 0.01 figure 4. on?resistance vs. drain current and gate voltage v gs, gate?t o?source voltage (volts) figure 5. on?resistance variation with temperature t j = 25 c 10000 0 t j = ?55 c v gs = 0 v 25 c r ds(on), drain?to?source resistance ( ) 3 v 25 3 0 2.6 v 4.5 v 0.02 2 1000 468 0.03 figure 6. drain?to?source leakage current vs. voltage 0 0.05 i d, drain current (amps) 0.01 0 r ds(on), drain?to?source resistance ( ) v gs = 4.5 v 15 10 10 t j = 25 c v gs = 10 v t j = 125 c t j = 150 c 4 5 v ds 10 v t j = 25 c i d = 7 a 20 5 10 10 4 3.5 v 10 v 6 v 5 15 0.04 0.05 2 0.02 0.03 0.04 5 5 6 t j , junction temperature ( c) 125 100 75 50 25 0 ?25 ?50 0.70 0.80 0.90 1.00 r ds(on) , drain?to?source resistance (normalized) 150 v gs = 10 v i d = 7 a 1.10 1.20 1.30 1.40 1.50 1.60 1.70 175
NVGS4141N http://onsemi.com 4 typical performance curves figure 7. capacitance variation figure 8. gate?to?source and drain?to?source voltage vs. total charge 0.9 2 0 v sd , source?to?drain voltage (volts) figure 9. resistive switching time variation vs. gate resistance i s , source current (amps) v gs = 0 v t j = 25 c 0.4 0 7 figure 10. diode forward voltage vs. current 0.8 0.6 5 6 gate?to?source or drain?to?source voltage (volts) c, capacitance (pf) 200 1200 10 0 5 10 5 t j = 25 c c iss c oss c rss 15 20 25 0 400 600 c iss c rss v ds = 0 v v gs = 0 v v ds v gs v gs , gate?t o?source voltage (v) 0 4 0 q g , total gate charge (nc) 10 8 i d = 7 a v dd = 15 v t j = 25 c v gs q gs r g , gate resistance (ohms) 1 10 100 1000 10 t, time (ns) v dd = 24 v i d = 7 a v gs = 10 v t r t d(on) t f t d(off) q gd qt 1 4 800 figure 11. maximum rated forward biased safe operating area 6 2 12 10 24 68 0.2 1000 100 1 3 0.3 0.7 0.5 0.1 0.1 1 100 v ds , drain?to?source voltage (volts) 0.01 100 r ds(on) limit thermal limit package limit 10 10 0 v v gs 20 v single pulse t c = 25 c 1 ms 100 s dc 0.1 1 10 ms i d , drain current (amps)
NVGS4141N http://onsemi.com 5 typical performance curves 2.5 2.25 2.0 1.75 1.5 1.25 1.0 0.75 0.5 0.25 0 0 20 40 60 80 100 120 140 160 t a , ambient temperature ( c) p d , power dissipation (w) figure 12. maximum power derating chart references is t j - max = 150 c r ja , t < 10 s, 1 sq in r ja , 1 sq in r ja , min pad t a , ambient temperature ( c) p d , power dissipation (w) figure 13. current derating chart 8.0 0 20 40 60 80 100 120 140 1 60 7.5 7.0 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 references is t j - max = 150 c r ja , t < 10 s, 1 sq in r ja , 1 sq in r ja , min pad 0.01 1000 0.01 0.1 1 10 100 1000 10 d = 0.5 r thja(t) , transient thermal response ( c/w) figure 14. thermal response 0.2 0.1 0.05 0.02 0.01 single pulse t, pulse time (s) 1 0.1 0.00001 0.0001 0.001 0.000001 100
NVGS4141N http://onsemi.com 6 package dimensions tsop?6 case 318g?02 issue v style 1: pin 1. drain 2. drain 3. gate 4. source 5. drain 6. drain 23 4 5 6 d 1 e b e1 a1 a 0.05 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. maximum lead thickness includes lead finish. minimum lead thickness is the minimum thickness of base material. 4. dimensions d and e1 do not include mold flash, protrusions, or gate burrs. mold flash, protrusions, or gate burrs shall not exceed 0.15 per side. dimensions d and e1 are determined at datum h. 5. pin one indicator must be located in the indicated zone. c *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* dim a min nom max millimeters 0.90 1.00 1.10 a1 0.01 0.06 0.10 b 0.25 0.38 0.50 c 0.10 0.18 0.26 d 2.90 3.00 3.10 e 2.50 2.75 3.00 e 0.85 0.95 1.05 l 0.20 0.40 0.60 0.25 bsc l2 ? 0 1 0 1.30 1.50 1.70 e1 e recommended note 5 l c m h l2 seating plane gauge plane detail z detail z 0.60 6x 3.20 0.95 6x 0.95 pitch dimensions: millimeters m p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 NVGS4141N/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any part icular purpose, nor does sci llc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer s hall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner.
|
